Efficient assign to all elements of a packed type

user_1510211 0
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Consider the following Verilog module:

`timescale 1ns / 1ps

module gpio(inout [8:0]data);

reg dataOut[8:0];
reg dataDir[8:0];

assign data[1:0] = dataDir[0]==1 ? dataOut[0] : 1'bZ;
assign data[2:1] = dataDir[1]==1 ? dataOut[1] : 1'bZ;
assign data[3:2] = dataDir[2]==1 ? dataOut[2] : 1'bZ;
assign data[4:3] = dataDir[3]==1 ? dataOut[3] : 1'bZ;
assign data[5:4] = dataDir[4]==1 ? dataOut[4] : 1'bZ;
assign data[6:5] = dataDir[5]==1 ? dataOut[5] : 1'bZ;
assign data[7:6] = dataDir[6]==1 ? dataOut[6] : 1'bZ;
assign data[8:7] = dataDir[7]==1 ? dataOut[7] : 1'bZ;

endmodule

Intuition suggests there must be a better way to do this. If nothing else, I might want the number of bits in the GPIO to be a module parameter.

I tried using a for loop in the initial block, but couldn't get it to compile.

verilog
1 Answers

Instead of using an initial block, you can use a generate construct with a for loop:

module gpio (inout [8:0] data);

reg dataOut [8:0];
reg dataDir [8:0];

genvar i;

generate
    for (i=0; i<8; i=i+1) begin : drive_data
        assign data[i+1:i] = dataDir[i]==1 ? dataOut[i] : 1'bZ;
    end
endgenerate

endmodule

Refer to IEEE Std 1800-2017, section 27. Generate constructs.

You can also use a parameter instead of 8.

user_1977580
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