Error: (vlog-2110) Illegal reference to net "code"

user_16438782 0
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I have tried this code, but it shows the error:

gray_counter\gray_counter.v(2): (vlog-2110) Illegal reference to net "code"

module gray_counter(code,clk,rst,count);//module declaration
 input [2:0]code=3'b000;
 input clk,rst;
 output reg count;
 reg [2:0]conv_code;
always@(posedge clk , posedge rst)
 begin
if(rst)
 begin
 count=0;
 end
 else
 begin
 conv_code={code[0],code[0]^code[1],code[1]^code[2]};//converting binary code to gray 
 case(conv_code)
 3'b000:count=count+1;
 3'b001:count=count+1;
 3'b011:count=count+1;
 3'b010:count=count+1;
 3'b110:count=count+1;
 3'b100:count=count+1;
 3'b101:count=count+1;
 3'b111:count=count+1;
 default:count=count+0;
 endcase
 end
 end
endmodule
vlsi system-verilog verilog
2 Answers

It is illegal to assign a value to an input port within a module. Change:

 input [2:0]code=3'b000;

to:

 input [2:0]code;

You may only drive values from outside the module, for example, in a testbench module.

Some simulators will give you more specific help. I see this with VCS:

Error-[V2KIIAD] Invalid initialization at declaration
  Source info:  input [2:0]code=3'b000;
  Non-output port 'code' cannot be initialized at declaration.

You can try your code on multiple simulators if you sign up for a free account on edaplayground.

user_1977580

Verilog does not allow ports to have default values. To be Verilog complient, change input [2:0]code=3'b000; to input [2:0]code; and never assign code inside you gray_counter module.

SystemVerilog does allow it with ANSI style module headers per IEEE1800-2012 § 23.2.2.2 ANSI style list of port declarations. Same section for with the newer IEEE1800-2017. I could not fined examples in the LRMs, but it is clear form the syntax. I didn't find they same syntax in the older IEEE1800-2005. I didn't see the LRMs suggest default assignment is legal for non-ANSI headers; however I did noticed that simulators that support defaults with ANSI module headers are also supporting non-ANSI.

To enable SystemVerilog parsing, change the file extension from .v to .sv. Note that some simulators only supported a limited subset of SystemVerilog features. Ports with default values may not be supported on your simulator or synthesizer. If not, you must remove the default assignment.

Normally you want to drive all your inputs where it is instantiated. By giving assigning a default to an input, you make the connection optional. This is not common practice in the industry, partly because the full tool chain (simulator, synthesizer, linter, etc.) need to support it, and partly because coding/debugging practices.

With SystemVerilog you can assign an input a default, but in most cases you should not.

user_19597320
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