Need help to auto indent in verilog or systemverilog code in VIM

user_16436878 0
Viewed 690
initial begin
if () begin
a=b;
c=d;
end
else begin
c=d;
c=a;
end
end

I have already tried, gg=G or selecting code and = is not working. Could you please help me here. code is unreadable.

system-verilog verilog vim
1 Answers

You can set the filetype to verilog by :set filetype=verilog. Or you can save the file as tmp.v and reopen it.

Below is from $VIMRUNTIME/filetype.vim which defines the relationship between filetype and file extension.

" Vera
au BufNewFile,BufRead *.vr,*.vri,*.vrh      setf vera

" Verilog HDL
au BufNewFile,BufRead *.v           setf verilog

" Verilog-AMS HDL
au BufNewFile,BufRead *.va,*.vams       setf verilogams

" SystemVerilog
au BufNewFile,BufRead *.sv,*.svh        setf systemverilog

" VHDL
au BufNewFile,BufRead *.hdl,*.vhd,*.vhdl,*.vbe,*.vst,*.vho  setf vhdl
user_51546010
Related