Disable statement not executing at a particular value

user_9031651 0
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enter image description hereI have written a code for counter and i'm implementing the disable statement. The counter has to count for particular value and exit the block once it reaches the value.

Here is the code:

module counter(
    );
    parameter number_of_count = 37;
    
    reg clk;
    integer count;
    
    initial
        begin
            count = 5;
            clk = 1'b0;
            forever #10 clk = ~clk;
        end
    
    always @(posedge clk)
        begin: this_block
            count = count + 1;
            $display ($time, " The present count is %d", count);
                repeat (number_of_count == count)
                    begin
                        count = 5;
                        disable this_block;
                    end
        end 
endmodule

I am not sure what I am missing.

system-verilog verilog
1 Answers

A simpler way is to use a while loop:

module counter;
    parameter number_of_count = 37;
    
    reg clk;
    integer count;
    
    initial
        begin
            count = 5;
            clk = 1'b0;
            forever #10 clk = ~clk;
        end
    
    initial begin
        while (count < number_of_count) begin
            @(posedge clk);
            count = count + 1;
            $display ($time, " The present count is %d", count);
        end
    end
endmodule

In your code, the block named this_block is executed at every posedge of clk. Your disable simply disables the current instance of the block execution. Since it is the last statement in the block, you really don't see any effect of the disable. The block is re-enabled on every posedge of clk. This is an unusual usage of disable. Refer to IEEE Std 1800-2017, section 9.6.2 Disable statement.

Note: disable is rarely used, and I recommend against trying to use it here.

user_1977580
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