I'm trying to decipher the following line of code in Verilog:
assign ASIC_error_flag = (StartTransfer & ~Bank_Slct[IO_Config_P2[13:12]]);
I suspect it might be a compare between the negated bus "Bank_Slct" and bits 13 through 12 of the bus IO_Config_P2, but I've never seen a bus inside of a bus like that before. What is this supposed to equate to?
The inner square brackets are used to select a portion of the IO_Config_P2 signal, and the outer brackets are in turn used to select a portion of the Bank_Slct signal.
Let's assume you declared Bank_Slct like a memory of 4 bytes:
reg [7:0] Bank_Slct [0:3];
In this case, you need a 2-bit signal to select one of the 4 bytes (like a memory address). The expression, IO_Config_P2[13:12], is the 2-bit select signal.
When IO_Config_P2[13:12] is equal to 2'b00, you are selecting byte Bank_Slct[0].
When IO_Config_P2[13:12] is equal to 2'b01, you are selecting byte Bank_Slct[1], etc.
An alternate approach would have been to create a separate signal (sel), then use that:
wire [1:0] sel = IO_Config_P2[13:12];
assign ASIC_error_flag = (StartTransfer & ~Bank_Slct[sel]);
Refer to IEEE Std 1800-2017, section 7.4.4 Memories.