Does the Condition Operator Evaluate Bitwise for indexed part selection

user_14317869 0
Viewed 104

I wish to choose between bits of two indexed part selections using the values of each of the bits of another indexed part selection. Put in code that looks like:

output[idx*WIDTH+:WIDTH] = (condition[idx*WIDTH+:WIDTH]) ? (expression1[idx*WIDTH+:WIDTH) : expression2[idx*WIDTH+:WIDTH];

e.g. Looking at a single bit, if condition[idx*WIDTH] = 1 I want output[idx*WIDTH] to contain the value of expression1[idx*WIDTH] and if condition[idx*WIDTH] = 0, I want output[idx*WIDTH] to contain the value of expression2[idx*WIDTH].

Is this legal in System Verilog? If not, is there a better way to achieve the same functionality while keeping the indexed part select for the buses?

system-verilog verilog conditional-operator
1 Answers

The conditional expression (or predicate) is Boolean—it is true or false. To evaluate the predicate bitwise, you can either use a foreach loop

for(int I=idx*WIDTH;I<(idx+1)*WIDTH;I++)
    output[I] = condition[I] ? expression1[I] : expression2[I];

or an equivalent mux equation:

output[idx*WIDTH+:WIDTH] = 
    condition[idx*WIDTH+:WIDTH] & expression1[idx*WIDTH+:WIDTH) |
    ~condition[idx*WIDTH+:WIDTH] & expression2[idx*WIDTH+:WIDTH];
user_27556070
Related