7-segment decoder does not have errors, but test is failing

user_15913819 0
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Below is my code for 7-segment decoder:

module decoder(
  input  i_A,
  input  i_B,
  input  i_C,
  input  i_D,

  output o_1,
  output o_2,
  output o_3,
  output o_4,
  output o_5,
  output o_6,
  output o_7
);
reg din;
reg dout;

always @* begin
  case(din)
    4'd0 : begin dout = 7'b0111111; end
    4'd1 : begin dout = 7'b0000110; end
    4'd2 : begin dout = 7'b1011011; end
    4'd3 : begin dout = 7'b1001111; end
    4'd4 : begin dout = 7'b1100110; end
    4'd5 : begin dout = 7'b1101101; end
    4'd6 : begin dout = 7'b1111101; end
    4'd7 : begin dout = 7'b0000111; end
    4'd8 : begin dout = 7'b1111111; end
    4'd9 : begin dout = 7'b1101111; end 
    default: dout = 7'b0000000;
  endcase
end

The code does not have any errors. But, when I test it on testbench, the test fails. Could someone help me? One of the tests on the test bench is below. I thought the condition for the test is satisfied, but apparently it is not. From the test bench, I think it means that sol_cnt increases by 1 if dout is equal to the parameter. Am I wrong about this? I am not sure what I have to fix from here because there is no error, but the tests just fail.

reg  [3:0] din;
wire [6:0] dout;

reg  [3:0] sol_cnt;

parameter SOLUTION_0 = 7'b0111111;

decoder u_decoder (
  .i_A ( din[0]  ),
  .i_B ( din[1]  ),
  .i_C ( din[2]  ),
  .i_D ( din[3]  ),

  .o_1 ( dout[0] ),
  .o_2 ( dout[1] ),
  .o_3 ( dout[2] ),
  .o_4 ( dout[3] ),
  .o_5 ( dout[4] ),
  .o_6 ( dout[5] ),
  .o_7 ( dout[6] )
);
din     = 0;
sol_cnt = 0;

din = 0;
  #10;
  if (dout==SOLUTION_0) begin
    $display ("Case 0 is passed");
    sol_cnt = sol_cnt + 1;
  end
  else begin
    $display ("Case 0 is failed");
  end
verilog
1 Answers

The decoder module has undriven output ports and unconnected input ports. Since your testbench uses bus signals for these, you might as well use bus ports:

module decoder(
    input [3:0] din,
    output reg [6:0] dout
);

always @* begin
  case(din)
    4'd0 : begin dout = 7'b0111111; end
    4'd1 : begin dout = 7'b0000110; end
    4'd2 : begin dout = 7'b1011011; end
    4'd3 : begin dout = 7'b1001111; end
    4'd4 : begin dout = 7'b1100110; end
    4'd5 : begin dout = 7'b1101101; end
    4'd6 : begin dout = 7'b1111101; end
    4'd7 : begin dout = 7'b0000111; end
    4'd8 : begin dout = 7'b1111111; end
    4'd9 : begin dout = 7'b1101111; end 
    default: dout = 7'b0000000;
  endcase
end
endmodule

In the testbench, the dut instance is changed to:

decoder dut (
    .din   (din),
    .dout  (dout)
);

The code runs and passes on edaplayground.

user_1977580
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