Verilog -- "and reduction" & duty cycle

Question

I am studying this Verilog file:

`default_nettype none

module stroboscope(i_clk, o_led);
    
    input wire i_clk;
    output wire o_led;

    reg [19:0] counter;
    initial counter = 0;

    always @(posedge i_clk)
        begin
            counter <= counter + 1'b1;
        end
    
    assign o_led = &counter[19:15];

endmodule

I figured out already that if I change the assign from it's current state to what is shown, below frequency of blinking LED o_led remains constant while it's duty cycle is increased to 100% (when it is turned on):

assign o_led = &counter[19:19];

It is possible to decrease the duty cycle now by setitng the same line to:

assign o_led = &counter[19:17];

Again... by setitng the same line to:

assign o_led = &counter[19:15];

And finally setting the same line as shown below will make a duty cycle of 0%:

assign o_led = &counter[19:0];

So how does unary & operator that represents a "and reduction" achieve this in the presented case?

I know a simple example of how this works i.e.

&`4b1101 = 0

The "and reduction" looks like this:

But, the example is much more complex, and I don't understand.

user_197758 · Answer

&counter[19:15]

is the same as:

counter[19] & counter[18] & counter[17] & counter[16] & counter[15]

The reduction-AND operator just does a bit-wise AND of each of its bits. So, your o_led signal is only high when all these 5 bits of counter are high, as between the cursors in the following diagram (click on the image to enlarge):

The pulsewidth of o_led matches that of the LSB in your reduction-AND expression. In my code above, the LSB is 15. If you change the LSB to 16, the pulsewidth doubles.

Verilog -- "and reduction" & duty cycle

1 Answers