Error (10170): Verilog HDL syntax error at CRC_configurable.v(62) near text: "integer"; expecting "end"

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I'm working with Quartus Prime Lite Edition and having a case statement with:

S2: begin
            dat[WID_DAT-1 :1] <= dat[WID_DAT-2 :0];
            dat[0] <= 0;
            crc[0] <= crc_temp[0];
            integer i;
            for (i = 1; i < WID_CRC; i = i+1) begin
                crc[i] <= crc_temp[i] ^ crc[i-1];
            end
            
            if(count != 0) begin
                r_ns <= S2;
                count <= count -1;
            end
            
            else begin
            r_ns <= S_DONE;
            done <= 1;
            end
        end

and get the error message when I Start Anlysis & Elaboration:

Error (10170): Verilog HDL syntax error at CRC_configurable.v(62) near text: "integer"; expecting "end".

Why is this so, and how should I avoid it?

verilog case for-loop
1 Answers

You must not declare an integer in the middle of a begin/end block. You could move the integer declaration line outside of the always block (before it).

integer i;

always ... 
...
S2: begin
            dat[WID_DAT-1 :1] <= dat[WID_DAT-2 :0];
            dat[0] <= 0;
            crc[0] <= crc_temp[0];
            for (i = 1; i < WID_CRC; i = i+1) begin
                crc[i] <= crc_temp[i] ^ crc[i-1];
            end

Or, if you give your begin block a name, you should be able to declare the integer immediately after the begin line.

user_1977580
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