How to get rid of Syntax error near "or" in Verilog

user_15609680 0
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I have recently started learning Verilog.
I am trying to build a Full Adder using task

task fullAdder(input a, b, c_in, output reg sum, c_out);
   reg x, y, z;
   begin
      halfAdder H1(x, y, a, b);
      halfAdder H2(sum, z, c_in, x);
      or M3(c_out, y, z);
   end
endtask

task halfAdder(input a, b, output sum, c_out);
   xor M1(sum, a, b);
   and M2(c_out, a, b);
endtask

I don't know what is wrong in my code, but it is giving errors like:

Syntax error near "or".
Syntax error near "xor".
Syntax error near "and".
task verilog syntax-error
1 Answers

You must not place instances inside a task; they should be in a module instead. Also, you should remove the reg type from the output ports, and change the internal reg to wire:

module fullAdder(input a, b, c_in, output sum, c_out);
   wire x, y, z;
   begin
      halfAdder H1(x, y, a, b);
      halfAdder H2(sum, z, c_in, x);
      or M3(c_out, y, z);
   end
endmodule

module halfAdder(input a, b, output sum, c_out);
   xor M1(sum, a, b);
   and M2(c_out, a, b);
endmodule

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user_1977580
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