I've been studying Verilog for a while and recently came across a kind of statement that I do not understand. Here is an example:
reg s_axis_data_tready_reg = 1'b0, s_axis_data_tready_next;
Looks like a concatenation but doesn't have the curly brackets surrounding the two items separated by a comma. This statement compiles with no error. What does this statement do?
This statement declares 2 1-bit signals as type reg, and it also initializes one of them to 1'b0 (s_axis_data_tready_reg). The other (s_axis_data_tready_next) has the value x (unknown), which is the default value for a reg.
module tb;
reg s_axis_data_tready_reg = 1'b0, s_axis_data_tready_next;
initial begin
#1 $display("reg=%b, next=%b", s_axis_data_tready_reg, s_axis_data_tready_next);
end
endmodule
This outputs:
reg=0, next=x
Since it does not use curly braces: {}, it is not a concatenation.
Your single line can be also written as 2 lines:
reg s_axis_data_tready_reg = 1'b0;
reg s_axis_data_tready_next;