Writing random data to a RAM in a testbench

I am working with RAM in Verilog, and I need to implement a test bench where I will confirm the correct operation of the three memory processes (write data, read data and read commands). I have written a testbench where it seems to be writing and reading some integer numbers, but is there any way to fill the memory with words or strings to be more clear randomly?

This is my testbench:

module ramtest();
  
parameter WORD_SIZE=8;
parameter ADDR_WIDTH=8;
parameter RAM_SIZE=1<<ADDR_WIDTH;
  
reg we;
reg re;
reg [ADDR_WIDTH-1:0] addr;
reg [ADDR_WIDTH-1:0] instraddr;
reg [WORD_SIZE-1:0] datawr;
reg Clk;
  
reg [WORD_SIZE-1:0] mem[RAM_SIZE-1:0];
  
wire [WORD_SIZE-1:0] datard;
wire [WORD_SIZE-1:0] instrrd;
  
MCPU_RAMController raminst (.we(we),.datawr(datawr),.re(re),.addr(addr),.datard(datard),.instraddr(instraddr),.instrrd(instrrd));
integer i;
initial begin 
   we=0;
   datawr=0;
   instraddr=0;
   addr=1;
   
   
   #20;
   for(i=0;i<RAM_SIZE;i=i+1) begin
     datawr=i;
     addr=i-1;
     #10;
   end
   we=0;
   addr=1;
   instraddr=0;
   for(i=0;i<RAM_SIZE;i=i+1) begin
     
     addr=i-1;
     #10;
   end
    
end
 
endmodule

And here is the RAM controller code where I need to test:

module MCPU_RAMController(we, datawr, re, addr, datard, instraddr, instrrd);
parameter WORD_SIZE=8;
parameter ADDR_WIDTH=8;
parameter RAM_SIZE=1<<ADDR_WIDTH;

input we, re;

input [WORD_SIZE-1:0] datawr;

input [ADDR_WIDTH-1:0] addr;
input [ADDR_WIDTH-1:0] instraddr;

output [WORD_SIZE-1:0] datard;
output [WORD_SIZE-1:0] instrrd;

reg [WORD_SIZE-1:0] mem[RAM_SIZE-1:0];


reg [WORD_SIZE-1:0] datard;
reg [WORD_SIZE-1:0] instrrd;

always @ (addr or we or re or datawr)
begin
  if(we)begin
    mem[addr]=datawr;
  end
  if(re) begin
    datard=mem[addr];
  end
end


always @ (instraddr)
begin
    instrrd=mem[instraddr];
end


endmodule