How to give a two dimensional array an initial value in verilog

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I'm working on an SPI module that involves one master and three slaves. In the test bench, I'd like to give each of the slaves a parallel load through a multidimensional array that's an input to the SPI module

reg [7:0] slaves_inload [3:1]= ?

I have no idea what should I write on the RHS of this. Suppose I'd like to pass : 8'b11101101, 8'b10101010 and 8'b10001000 for slaves [1], [2], [3], respectively.

system-verilog verilog
1 Answers

One way to initialize the array is as follows:

reg [7:0] slaves_inload [3:1] = '{8'b10001000, 8'b10101010, 8'b11101101};
                                 //    3            2            1

This syntax can be seen in the IEEE Std 1800-2017, section 10.9.1 Array assignment patterns.

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