Illegal assignment pattern. the number of elements (1) does not match with type's wirth (2). in system verilog

user_13471306 0
Viewed 466

I am attaching the case with it.

module top;
    reg [1:0] arr; 

    reg [2:0] arr_asgn;

    assign arr = {'{ default: arr_asgn[2] }};
endmodule
system-verilog verilog
2 Answers

this is syntactically incorrect. You have an assigment pattern inside a concat {}. There is no assignment context there. You have to remove external braces:

assign arr = '{ default: arr_asgn[2] };
user_11438500

This is syntactically incorrect. As you are trying to assign a 2-D array to 1-D packed array. According to LRM either right-hand side should be 2-d like this.

  arr[1:0][1:0];
  assign arr = '{'{default:1}, '{default:0} }

or it should be 

 assign arr = '{default:1}
user_71471320
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