How does %m work in $display system task?

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I want to understand the usage of %m in the $display system task in Verilog.

This is sample code given in the book. It would be better if someone explains this with more examples as it seems unclear in the book.

//the highest-level module called top. No argument is required. This
//is a useful feature)
$display("This string is displayed from %m level of hierarchy");
-- This string is displayed from top.p1 level of hierarchy
verilog
1 Answers

The free IEEE Std 1800-2012, section 21.2.1.6 Hierarchical name format states:

The %m format specifier does not accept an argument. Instead, it causes the display task to print the hierarchical name of the design element, subroutine, named block, or labeled statement that invokes the system task containing the format specifier. This is useful when there are many instances of the module that calls the system task.

Here is an example:

module top;
   buff b0 (.buf_in(1'b0), .buf_out());
endmodule

module buff (
   input  buf_in,
   output buf_out
);
   wire  a;
   inv i0 (.in(buf_in), .out(a      ));
   inv i1 (.in(a     ), .out(buf_out));
   initial $display("Inside hierarchy %m");
endmodule

module inv (
   input  in,
   output out
);
   assign out = ~in;
   initial $display("Inside hierarchy %m");
endmodule

Outputs:

Inside hierarchy top.b0
Inside hierarchy top.b0.i0
Inside hierarchy top.b0.i1
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