Cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

user_10213925 0
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This code fails to compile and gives the error as in the title at the "if(overflow)" line. 

always @(posedge clk or negedge overflow) begin
    if(overflow)
        count_posedge = count_posedge + 1;
    else
        count_posedge = 0;
end

I've somewhere on the internet that I must change it like this:

always @(posedge clk or negedge overflow) begin
    if(~overflow)
        count_posedge = 0;
    else
        count_posedge = count_posedge + 1;
end

...and it works perfectly.

From my understanding, the 2 code should behave the same. What's the problem with the first one?

verilog
1 Answers

This is more likely an issue with your synthesizer then your simulator. The likely problem is that the first code does not match any of it's templates for a synchronous flip-flop with asynchronous reset.

The common coding practice is to assign your reset logic before any other logic. This coding practice has been around for decades. I assume the rational behind this particular coding practice stems from:

  • Reset logic is critical from many designs; especially as designs get larger and more complex. It is put at the top for it importance and the fact that it usually fewer lines of code then the synchronous logic.
  • Early synthesizers were very limited and could only synthesize specific code structures.
  • The coding style has become a precedence. No one is going to change it unless you can convince and prove something else is superior or has specific advantages.

In your case, your synthesizer is doing a lint check and has determined your code is not following the conventional coding practices. The creator of your synthesizer has decided to only support the common coding structure and there is little incentive to change.

FYI: you should be assigning synchronous logic with non-blocking assignments (<=). Blocking assignments (=) should be used for combinatonal logic. If you do not follow proper coding practices you increase the risk of introducing race-conditions, RTL vs gate mismatch, and other bugs.

user_19597320
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