VHDL Aggregate Assignment Using Aliases

I am having some trouble using aggregates in my VHDL test bench (short hand shown below).

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all    

entity TB is 
end entity;

architecture RTL of TB is
    -- constant(s)
    constant  CLK_PERIOD    : time                         := 10 ns; -- 100 MHz
    -- signal(s)
    signal    CLK           : std_logic                    := '0';
    signal    nRST          : std_logic                    := '1';
    signal    CONFIG_REG    : std_logic_vector(7 downto 0) := (others => '0');
begin
    -- clock driver
    CLK  <= NOT CLK after (CLK_PERIOD / 2.0);

    -- main process
    process
    begin
        -- reset driver...
        nRST  <= 
            '1', 
            '0' after (CLK_PERIOD * 1);

        -- set initial configuration...
        CONFIG_REG <= (
            6           =>  '1',     
            3 downto 2  => "01", 
            7 | 0       =>  '1', 
            others      =>  '0'
        );

        -- do test-bench stuff...

        -- update configuration...
        CONFIG_REG <= (
            6           =>  '0',     
            3 downto 2  => "10", 
            7 | 0       =>  '1', 
            others      =>  '0'
        );

        -- do more test-bench stuff...
    end process;
end architecture;

I really want to 'name' the parts of the configuration register so that it actually reads well.

So I want to say:

Bit[6]   = ENABLE
Bit[3:2] = MODE
Bit[7|0] = READY_DONE

I know that I can use a constant for the 6:

constant  ENABLE : integer := 6;

and then my code looks like this:

CONFIG_REG <= (
    ENABLE      =>  '1',     
    3 downto 2  => "01", 
    7 | 0       =>  '1',
    others      =>  '0'
);

But I've been stumped to try and get the range 3 downto 2 and the 7|0 named so that the code looks like:

CONFIG_REG <= (
    ENABLE      =>  '1',     
    MODE        => "01", 
    READY_DONE  =>  '1',
    others      =>  '0'
);

I thought I might be able to accomplish this using aliasing and I've been looking at the VHDL Golden Reference Guide (p.15) which has been pretty helpful as far as understanding aliasing and ranges go, but I still cannot figure out how to name a range itself or an 'or'(|) of values.

Currently I have the below 'hack', which I'm not really fond of...

constant ENABLE :  integer := 6;
alias    MODE   is CONFIG_REG(3 downto 2);
-- what to do about the OR though???

CONFIG_REG <= (
    ENABLE      =>  '1',     
    MODE'RANGE  => "01", 
    7 | 0       =>  '1',
    others      =>  '0'
);

I really want to make my test-bench readable so that when I look at it 6 mo. from now, I'll know what it's doing without having to go and figure out "Now what was bit[6] again???" or in the event I have to hand off my code to another developer, they can easily get an idea of what I was trying to accomplish.

Any help / advice would be appreciated on how to do this.

Thanks for reading.

EDIT: Fixed the 7 | 0 to be valid:

Invalid:

7 | 0       =>  "10",

Valid:

7 | 0       =>  '1',