I'd like to be able to continuously force a signal down in my testbench hierarchy. Here is a simple example illustrating how I've been doing this in my test benches.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity double_inverter is
port(
a : in std_logic;
z : out std_logic
);
end double_inverter;
architecture x of double_inverter is
signal b : std_logic;
begin
b <= not a;
z <= not b;
end architecture x;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity inverter_tb is
end inverter_tb;
architecture y of inverter_tb is
signal z : std_logic;
signal clk : std_logic := '0';
begin
clk <= not clk after 5 ns;
dut : entity work.double_inverter
port map(
a => '0',
z => z
);
continuous_stim : process(clk)
begin
<< signal dut.b : std_logic >> <= force clk;
end process;
end architecture y;
This works in Modelsim 10.4b i.e. signal b in the double_inverter instance will be set by clk and not signal a, but is there a better way to control external name signals?
Thanks for your help.