I am having a very frustrating experience with my first week learning Verilog.
I am trying to compile the below code - from mipsalu.v
module MIPSALU (ALUctl, A, B, ALUOut, Zero);
input [3:0] ALUctl;
input [31:0] A,B;
output reg [31:0] ALUOut;
output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere
always @(ALUctl, A, B) //reevaluate if these change
case (ALUctl)
0: ALUOut <= A & B;
1: ALUOut <= A | B;
2: ALUOut <= A + B;
3: ALUOut <= A ^ B;
6: ALUOut <= A – B;
7: ALUOut <= A < B ? 1:0;
12: ALUOut <= ~(A | B); // result is nor
default: ALUOut <= 0; //default to 0, should not happen;
endcase
endmodule
When I try to compile this using iverilog -o test mipsalu.v, iverilog tells me
mipsalu.v:13: syntax error
I give up.
When I remove the offending line and compile again, there are no errors-
module MIPSALU (ALUctl, A, B, ALUOut, Zero);
input [3:0] ALUctl;
input [31:0] A,B;
output reg [31:0] ALUOut;
output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere
always @(ALUctl, A, B) //reevaluate if these change
case (ALUctl)
0: ALUOut <= A & B;
1: ALUOut <= A | B;
2: ALUOut <= A + B;
3: ALUOut <= A ^ B;
//6: ALUOut <= A – B;
7: ALUOut <= A < B ? 1:0;
12: ALUOut <= ~(A | B); // result is nor
default: ALUOut <= 0; //default to 0, should not happen;
endcase
endmodule
Any insight would be much appreciated. Thank you!
Edit: it's worth mentioning that I am running version 10 of Icarus Verilog on Windows 8.1 using MinGW/MSYS