Division in verilog

user_843036 0
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I am teaching myself verilog. The book I am following stated in the introduction chapters that to perform division we use the '/' operator or '%' operator. In later chapters it's saying that division is too complex for verilog and cannot be synthesized, so to perform division it introduces a long algorithm.

So I am confused, can't verilog handle simple division? is the / operator useless?

verilog
10 Answers

if you want the synthesizable code you can use the Divison_IP or you can use the right shifting operator for some divisions like 64/8=8 same 64>>3 = 8.

user_128964920

Division isn't simple in hardware as people spent a lot of time in an efficient and fast multiplier as an example. However, you can do divid by 2 easily by right shifting one bit in hardware.

user_61186460
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