Array manipulation in systemverilog

digitalman 0
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logic [M-1:0] x [N-1:0]; // x is N number of rows and M number of bits
genvar i;
genvar j;

for (i=0; i<N; i++) begin
     for (j=0; j<M; j++) begin
         x[i][j] = $random;
     end
end

In the real code, it is not random, but this is an input bit. But the same error is introduced which is

token is '['
x[i][j]

making a pointer on the second [

What is the mistake?

verilog system-verilog signal-processing filter
2 Answers

Since you have a generate construct, you can not have a bare assignment statement there. Use the assign keyword:

for (i=0; i<N; i++) begin
     for (j=0; j<M; j++) begin
         assign x[i][j] = $random;
     end
end
toolic0

It is strange that you use a generate construct to initialize an array in a purely behavioral way. The construct is used to simply replicate verilog statements, such as assign or module instances.

Usually such initialization is done in initial blocks, like the following:

initial begin
  for (int i=0; i<N; i++) begin
     for (int j=0; j<M; j++) begin
         x[i][j] = $random;
     end
  end
end
userOAN40
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