What does the expression [ lsb_base_expr +- width_expr ] syntesize to?

nanoeng 0
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While searching for solutions related to the Verilog code error message 'range must be bounded by constant expressions", I came across answers that pointed to the SystemVerilog LRM's use of part-select addressing such as this earlier post.

I successfully applied such descriptions for most of my vector assignments.

There was, however, a description that the tool didn't like. I searched for an alternative and found that the expression [ lsb_base_expr +- width_expr ] could work. I tried it and it seems to be working. I want to find where the LRM describes it or if it is somehow something I should not use for synthesis purposes.

verilog system-verilog
2 Answers

Sections 7.4.6 Indexing and slicing of arrays and 11.5.1 Vector bit-select and part-select addressing both describe this syntax.

This gets synthesized as a barrel shifter. The fact that you cannot have variable width operands is a language restriction, unrelated to synthesis.

dave_590

11.5.1 Vector bit-select and part-select addressing

An indexed part-select is given with the following syntax:

logic [15:0] down_vect;
logic [0:15] up_vect;
down_vect[lsb_base_expr +: width_expr]
up_vect[msb_base_expr +: width_expr]
down_vect[msb_base_expr -: width_expr]
up_vect[lsb_base_expr -: width_expr]

The msb_base_expr and lsb_base_expr shall be integer expressions, and the width_expr shall be a positive constant integer expression. Each of these expressions shall be evaluated in a self-determined context. The lsb_base_expr and msb_base_expr can vary at run time.

userOAN40
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