Calculating a parameter from another parameter via a function prevents verilog IP from packaging

I have a module to which I configure with a parameter WIDTH, intialized to 16:

module ma_width #(parameter WIDTH =16)(
   new_sample,
   en,
   sample_out, 
   clk,
   reset_b
   );

Based on that width, I use a function to determine the number of overflow bits I need to size a register :

function integer log2(input integer v); 
begin 
  log2=0; 
   while(v>>log2) 
     log2=log2+1; 
end
endfunction

I then define another parameter, and it is this one that fails (I think) when I go to package the ip in Vivado:

  parameter ovflwbits=log2(WIDTH)-1;

My intent is to use this parameter when I declare a register, for example:

reg  [WIDTH+ovflwbits:0]  prevout;

The module works in simulation, and synthesizes. However, when I go to package it, I get the following errors:

Is there any way to do this? I want to be able to determine the overflow bits from the WIDTH parameter "automatically" instead of having to manually enter it at the time I configure the WIDTH parameter prior to synthesis and implementation...