Problem in simulation of I2C Master with 24LC128 EEPROM from Microchip (VHDL/Verilog)

I want to interface the EEPROM 24LC128 which is available on my FPGA board. I have used an I2C master core from OpenCores in VHDL. For the simulation, i am using the Verilog Model of the EEPROM which is available on the Microchip website.

However, in the simulation of the core I always see an "X" driven to SDA line.

SDA Line control in the I2C Master:

sda <= 'Z' when sda_x = '1' else '0'; -- sda_x controls SDA line via tri-state buffer, 'Z' implies high cz of external pull-up resistors

SDA I/O BUFFER in Verilog EEPROM Slave

 // -------------------------------------------------------------------------------------------------------
//      1.14:  SDA Data I/O Buffer
// -------------------------------------------------------------------------------------------------------

   bufif1 (SDA, 1'b0, SDA_DriveEnableDlyd);

   assign SDA_DriveEnable = !SDA_DO & SDA_OE;
   always @(SDA_DriveEnable) SDA_DriveEnableDlyd <= #(tAA) SDA_DriveEnable;

Also, in the testbench I have added a weak pull-up to the SDA line:

Adds weak pull-up on SDA line for simulation purpose
 sda <= 'H';

Link to the Verilog Model: https://ww1.microchip.com/downloads/en/DeviceDoc/24xx128_Verilog_Model.zip

I cannot figure out why the signal SDA is driven to "X". Any help would be appreciated.

Thanks and Regards.