Retrieving data from array passed as argument in Verilog

I am trying to create a 2:1 multiplexer with gate-level modelling. For the multiplexer itself the code is here:

module mux2to1(x, s, f);
  input [0:1]x, s;
  output f;
  wire nots, prod1, prod2;
  not(nots, s);
  and(prod1, x[0], nots), (prod2, x[1], s);
  or(f, prod1, prod2);
endmodule

Am I using the arrays wrong, because the first 'and' gate to get 'prod1' I have is always returning 0. This is my test bench:

module testbench;
  reg a;
  wire f;
  mux2to1 tto1({1, 1}, a, f);
  initial begin
    a = 0;
    #100
    a = 1;
  end
endmodule

I understand that I need not use an array, but I need to scale this to a 16:1 mux, so I thought this is the best way. Here is a link to my EDA Playground that I am working at: https://www.edaplayground.com/x/YGyL