Verilog indexing through a vector by 4 bits

ZAKARIA BOUHANNA 0
Viewed 44

Please excuse my novice question.

I have a vector:

wire [WIDTH-1:0] data_in;

and would like to obtain only the bits highlighted below:

|63|....|31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|

So basically, skip 4LSB bits, then capture the following 8 bits, then skip 4 bits ..

The current code:

localparam WIDTH = 64;
wire [WIDTH*64-1:0] data_in;    
assign data_in[WIDTH*0+:WIDTH] = data_out;

I would like to know how to use this answer https://stackoverflow.com/a/18068296/20013745 to iterate through the bits as per above.

Many thanks

verilog
1 Answers

There are no syntax shortcuts for selecting non-contiguous bits in a single expression. You need to use a for loop either by creating a function containing it to use in the continuous assignment, or you can change the wire to a variable and use an always block.

integer i;
always @*
  for(i = 0;i<64/12;i=i+1);
      data_out[i*8+:8] = data_in[(4+i*12)+:8];
dave_590
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