SV Function to convert logic packed arrays of arbitrary value to string

ex1led 0
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I am trying to write a function that takes as input a logic[:] value of arbitrary length to a string. But I am unable to find a correct way of implementing it.

I have tried the following approach:

function string bin_to_string (input logic _bin_ [] );
    automatic string _str_;

    _str_ = "";
    for(int i=0; i< size; i++) begin
        automatic string tmpstr; 
        tmpstr.bintoa(_bin_[i]);
        _str_ = {_str_, tmpstr };
    end
    return _str_;
endfunction : bin_to_string

Which raises the following error:

Arg. 'bin' of 'bin_to_string': Cannot assign a packed type 'reg[3:0]' to an unpacked type 'reg $[]'.

Is such a thing i.e., creating a generic cast function for arbitrary length registers possible?

Thanks in advance

verilog system-verilog casting
1 Answers

The error message you show is from calling the function, not its implementation. You need to stream the packed array argument to an unpacked array.

mystring = bin_to_string( {>>{ input_arg }} );

Also, you have a typo in that size is never defined. But it would be easier to use foreach( _bin_[i] ) instead

dave_590
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