Does defining a vector before a single bit input affect the single bit?

destroyer806 0
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I am trying to define a module, but SystemVerilog thinks that my "works" is 3 bits. Does having that logic right after a 3-bit vector of "In" affect it? I am trying to connect to a test bench that instantiates this module but keep getting a port width mismatch. I put the error messages below (The message is from when I tried to do .In(In) etc.).

Module header:

module random
    (input logic [2:0] In, works,
    output logic [7:0] Out);

Test header:

module random_test;
    logic [2:0] In;
    logic works;
    logic [7:0] Out;

    random r(.In, .works, .Out);

Error:

Warning-[PCWM-W] Port connection width mismatch
tests.sv, 8
"random r( .In (In),  .works (works),  .Out (Out));"
The following 1-bit expression is connected to 3-bit port "works" of module 
"random", instance "r".
Expression: works
Instantiated module defined at: "random.sv", 4
Use +lint=PCWM for more details.


Warning-[PCWM-W] Port connection width mismatch
tests.sv, 8
"random r( .In (In),  .works (works),  .Out (Out));"
The following 8-bit expression is connected to 1-bit port "Out" of module 
"random", instance "r".
Expression: Out
Instantiated module defined at: "random.sv", 4
Use +lint=PCWM for more details.
verilog system-verilog
2 Answers

works is 3 bits because it inherits the [2:0] from the input declaration.

To get works to be a single bit, declare it using the input keyword:

module random
    (
    input logic [2:0] In,
    input logic works,
    output logic [7:0] Out
    );
endmodule

It does not give me a warning on EDA Playground.

toolic0

When you have a list of declarations separated by commas ,. Verilog has a set of implicit defaults that carry over from one declaration to the next. At a minimum, you need to explicitly add a datatype to works to reset the implicit data type back to a single bit.

module random
    (input logic [2:0] In, logic works,
    output logic [7:0] Out);

See section 23.2.2.3 Rules for determining port kind, data type, and direction in the IEEE 1800-2017 SystemVerilog LRM

dave_590
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