Is event can be used in design verilog code?

I am trying to implement a dual port memory in Verilog. The synthesize + analysis takes too long. It may be due to non-synthesizable construct in code. I am very confused about it. Does this mean we cannot use any non-synthesizable Verilog construct in our design code? The 'parameter' and 'for' are non-synthesizable construct, but the design code was compiled successfully when I used these constructs in some design coding.