VHDL: formal generic 'n' has no actual or default value?

I'm trying to simulate my VHDL component in Vivado and i'm receiving a compilation error: "formal generic 'n' has no actual or default value". I would appreciate any advice or solution to this error.

I have seen the issue VHDL: formal port 'portName' has no actual or default value and my error, although similar, does not seem related.

entity bit_tester is 
generic (N : integer);
port(in1 : in bit_vector (N-1 downto 0);
    out1 : out bit;
    out2 :out bit;
    out3 :out bit);
end bit_tester;

architecture behavioral of bit_tester is