Verilog vcs simulates if/else incorrectly but ternary operator correctly

I am writing a state machine in System Verilog and simulating using vcs and debugging with dve. When I use an if/else clause to assign my state information, I get this weird behavior.

COMPUTE: begin
    if (b_r == '0) begin
        state_next = gcd_pkg::COMPLETE;
        a_next = a_r;
        b_next = b_r;
    end else begin
        state_next = gcd_pkg::COMPUTE;
        a_next = b_r;
        b_next = a_r % b_r;
    end
end

dve identifies state_next as being assigned in the if block but a_next/b_next as being defined in the else block.

If I use tertiary operator instead,

COMPUTE: begin
    a_next =     (b_r == 0) ? a_r               : b_r             ;
    b_next =     (b_r == 0) ? b_r               : a_r % b_r       ;
    state_next = (b_r == 0) ? gcd_pkg::COMPLETE : gcd_pkg::COMPUTE;
end

dve indicates that all expressions are being assigned properly, (there is not mix/match in picking some values for b_r == 0 and some for b_r != 0

Does anyone have any experience with why vcs/dve would have this weird behavior?