Accidentally synthesizing combinatorial loop in sequential always block

I'm new to Verilog (HDLs in general), and am trying to write a simple PWM generator module in Verilog. The length/duty-cycle of the pulses should vary with the position input. My code is as follows:

`timescale 1ns / 1ps

module pwm_generator(
    input wire clock,
    input wire [7:0] position,
    output wire pwm
    );
    
    parameter full_pulse = 10;
    parameter full_period = 20;
    
    reg [7:0] clock_count = 0;
    
    
    always@(clock) begin
        if (clock_count < full_period-1) begin
            clock_count <= clock_count+1;
        end else begin
            clock_count <= 0;
        end
    end
    
    assign pwm = (clock_count < position*full_pulse/256);
    
endmodule

It simulates as expected, but when I try to synthesize/implement it in Vivado, I get the following errors:

[Synth 8-567] referenced signal 'clock_count' should be on the sensitivity list ["C:/Users/...":36]
[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition.

I'm guessing that this means it is attempting to synthesize my sequential clocked always block into some kind of combinational logic. Where did I go wrong, and how can I avoid this error? I feel like I'm missing something very basic.