Top Answers

1. What specifically marks an x86 cache line as dirty - any write, or is an explicit change required?
   8 votes
2. How does MIPS r10000 fetch hide instruction cache latency?
   6 votes
3. Aarch64 what is late-forwarding?
   5 votes
4. Why are CPU registers fast to access?
   4 votes
5. Way prediction in modern cache
   3 votes