x86

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Why does mulss take only 3 cycles on Haswell, different from Agner's instruction tables? (Unrolling FP loops with multiple accumulators)
user_83064890
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46
1
4291
micro-optimization sse x86 assembly c
How can I reconcile short conditional jumps with branch target alignments with `.align` in Delphi assembler?
user_69108680
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5
1
357
memory-alignment x86 assembly delphi
How to enable __fp16 type on gcc for x86_64
user_5042860
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17
1
11041
half-precision-float x86 gcc c c++
What does "r/m8" mean when used in instruction encoding tables?
user_80418270
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10
1
3703
x86 assembly
Why MOV AH,1 is not supported in 64 bit mode of intel microprocessor?
user_52547770
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3
2
1130
x86-64 x86 assembly
Can Hard and Soft-IRQ for the same network-packet be executed on different CPU-Cores?
user_15580370
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6
1
1481
interrupt x86 linux-kernel networking linux
Was there a P4 model with double-pumped 64-bit operations?
user_1491380
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5
1
750
x86-64 intel x86 cpu-architecture
Assembly BIOS call not working
user_77248510
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4
1
174
bios x86-16 bootloader x86 assembly
How many 1-byte NOPs can Skylake execute at one cycle
user_69108680
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8
3
1323
no-op alignment x86 assembly optimization
When to use ADOX instead of ADCX?
user_66741260
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7
1
560
adx x86 assembly
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