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Why is LOCK a full barrier on x86?
user_1332171
0
•
asked Feb 21, 2020
6
1
741
memory-barriers
x86
cpu-architecture
Unexpectedly high latency spikes measured with hwlat
user_12285729
0
•
asked Oct 28, 2019
2
0
146
preempt-rt
x86
real-time
linux
performance
Kernel.c not executing complete code [OS from scratch]
user_12284787
0
•
asked Oct 28, 2019
3
1
164
bootloader
osdev
kernel
x86
assembly
Does Skylake need vzeroupper for turbo clocks to recover after a 512-bit instruction that only reads a ZMM register, writing a k mask?
user_224132
0
•
asked Oct 26, 2019
10
1
622
avx512
micro-optimization
intel
x86
assembly
Long latency instruction
user_149138
0
•
asked Oct 25, 2019
3
2
387
microbenchmark
micro-optimization
x86
cpu-architecture
optimization
Storing a general purpose register in st0
user_149138
0
•
asked Oct 25, 2019
2
2
689
x87
x86-64
floating-point
x86
Problem with BIOS INT 13H (Read Sectors From Drive)
user_4159273
0
•
asked Oct 25, 2019
3
1
874
bios
bootloader
virtualbox
x86
assembly
AVX512BW: handle 64-bit mask in 32-bit code with bsf / tzcnt?
user_12202536
0
•
asked Oct 25, 2019
2
2
379
avx512
micro-optimization
32-bit
x86
assembly
Clang compiler (x86): 80 bit long double
user_12269605
0
•
asked Oct 24, 2019
4
0
522
x87
long-double
clang
x86
c++
Does SSE/AVX provide a means of determining if a result was rounded up?
user_10624355
0
•
asked Oct 23, 2019
4
1
349
avx
simd
sse
x86
rounding
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