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Am I correctly reasoning about cache performance?
user_4258629
0
•
asked Jul 31, 2020
3
1
113
perf
cpu-cache
x86
multithreading
c++
How Does BIOS initialize DRAM?
user_12650189
0
•
asked Jul 29, 2020
10
2
3268
bios
x86
assembly
post
What does the "D" stand for in 386's "D bit"?
user_738287
0
•
asked Jul 28, 2020
2
1
191
gdt
memory-segmentation
x86
assembly
terminology
Why did ld turn my 5 lines of library-less C into a 100MB binary?
user_815612
0
•
asked Jul 26, 2020
3
0
430
osdev
ld
x86
gcc
c
How to update GDT entries after initial loading?
user_13930270
0
•
asked Jul 25, 2020
2
1
167
i386
gdt
osdev
operating-system
x86
Why does my bootloader not load a byte from memory correctly?
user_815612
0
•
asked Jul 25, 2020
3
2
194
real-mode
bootloader
low-level
x86
assembly
If LDT does not exist in 64-bit architecture how are 32-bit systems that use it emulated on a 64-bit architecture?
user_12357180
0
•
asked Jul 24, 2020
2
1
243
gdt
x86-64
instruction-set
x86
assembly
How to determine the OS (linux or windows) just by using assembly? (x86)
user_7225528
0
•
asked Jul 23, 2020
3
0
161
x86
assembly
linux
security
windows
Inline asm fails to compile without optimization
user_4184203
0
•
asked Jul 21, 2020
4
1
265
inline-assembly
cpu-registers
x86
linux
c
Does cmpxchg write destination cache line on failure? If not, is it better than xchg for spinlock?
user_2945027
0
•
asked Jul 21, 2020
5
2
667
compare-and-swap
micro-optimization
cpu-cache
x86
assembly
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