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SPARC single-stepping mode
user_3521409
0
•
asked Sep 16, 2018
3
1
60
sparc
assembly
debugging
Is there a penalty when base+offset is in a different page than the base?
user_555045
0
•
asked Sep 16, 2018
14
2
950
micro-optimization
x86
assembly
performance
How to pass arguments in SPIM CLI's interactive debugging mode?
user_4558171
0
•
asked Sep 15, 2018
2
0
153
spim
mips
assembly
What does 'escape opcode' mean?
user_5744858
0
•
asked Sep 15, 2018
2
1
1056
opcode
machine-code
x86
assembly
encoding
MIPS pipeline stages
user_3719263
0
•
asked Sep 15, 2018
2
2
715
mips
pipeline
assembly
Questioning validity of PowerPC barriers in GCC-generated atomics
user_379897
0
•
asked Sep 14, 2018
6
0
245
powerpc
atomic
assembly
c
Why can the Rust compiler not optimize away the Err arm of Box::downcast?
user_3131852
0
•
asked Sep 13, 2018
10
1
479
llvm-codegen
compiler-optimization
rust
assembly
optimization
Copying a bool from a parameter to a global - comparing compilers output
user_214671
0
•
asked Sep 13, 2018
15
2
546
compiler-optimization
micro-optimization
x86
assembly
c++
GCC seemingly misses simple optimization
user_1072878
0
•
asked Sep 13, 2018
6
1
476
assembly
gcc
optimization
c++
Are CPU general purpose registers usually memory mapped?
user_8225902
0
•
asked Sep 13, 2018
4
1
4283
memory-mapping
arm
cpu-registers
assembly
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