MIPS pipeline stages

If an instruction doesn't need the MEM stage it won't drive any memory related signal in that stage but it still need to go through it.
It is a waste of time but still an improvement over non pipelined processing.

One idea for making the classic MIPS 5-stage machine skip MEM on demand is to add a datapath from EX to WB and add some logic.
If an R-type instruction comes after a load/store a conflict would arise:

IF ID EX MEM WB
   IF ID EX  WB <-- Conflict: two instructions in WB

The CPU could send the output of EX to both MEM and WB, plus the MEM stage would mask off the datapath from EX to WB when that stage is needed and would mask off the MEM - WB datapath when it is not needed.
This way when there is already an instruction in MEM, the next instruction in EX will go in MEM (and not WB) in the next cycle:

IF ID EX MEM  <-- Here EX-WB is masked (since MEM is used) and MEM-WB is allowed
   IF ID EX   <-- Can go to both MEM and WB but EX-WB is masked off


IF ID EX MEM WB  <-- So this instruction's next stage is WB (as usual)
   IF ID EX  MEM <-- This goes to MEM instead, so the pipe keeps flowing

If the previous instruction didn't need MEM, one stage can be skipped:

IF ID EX  <-- Here EX-WB is allowed (assume no prev instructions) and MEM-WB is not since (MEM was not used)
   IF ID 

IF ID EX WB <-- Instruction skips MEM stage since EX-WB was allowed
   IF ID EX <-- Next instruction, again, EX-WB is allowed since MEM was not used

IF ID EX WB <-- Done
   IF ID EX  WB <-- Stage MEM skipped

ADDENDUM

It's worth noting that in case of a conflict for the WB stack link in the very first example, it's better to stall the the whole pipeline for 1 cycle otherwise the conflict will never resolve and all the subsequent instructions will go through the MEM stage regardless their type.

With no stall:

mem = Useless MEM stage but necessary to avoid a WB confict
MEM = Instruction uses the MEM stage

IF ID EX MEM WB
   IF ID EX  mem WB
      IF ID  EX  mem Wb

If we introduce a stall of one cycle we resolve the conflict:

Lowercase names means stalled cycles

IF ID EX MEM WB
   IF ID EX  ex  WB
      IF ID  id  EX WB
         IF  if  ID EX WB
                 IF ID EX WB
                    IF ID EX WB

Notice how from the throughput point of view this optimisation don't really bring anything useful in.
The pipeline stabilises to a shorter length but if you compare this diagram with one where MEM is mandatory you get all the WB stages in the same cycles!
If A depends on B then A needs to wait for B to get to its WB stage (or EX if there is forwarding in the pipeline) and since the positions of the WB (or EX) stages is the same with or without this optimisation, it is not directly observable to the software (i.e. it has no benefit).

A shorter pipeline however consumes less energy and it's faster to refill after a flush but to really exploit the ability to skip a stage one need a superscalar CPU (that has more than one execution unit, so that EX and MEM can overlap).

Imagine an assembly line making a car. Some jeeps lest say will have the spare wheel installed on the back, some wont. to mimic a processor we assume that the assembly line is making different custom vehicles, rather than just one feature set for a while. So if the jeep with no wheel skips ahead it will run into the jeep in the next spot. So what happens, it simply doesnt get the wheel installed and it steps along in the pipe.

This a fundamental part of a pipeline or assembly line design. You define the steps, and everything goes linearly through those steps whether it uses that step or not. The POINT is to have multiple instructions/vehicles being processed at the same time. I car rolls out of the far end one every minute lets say, does tht mean it takes one minute to make a car? No we paralleled the process so that you are making many cars at once. Same with instructions the point is to parallelize it even if each step doesnt perform a function.

The key to the design is to make enough pipe stages long enough (I wouldnt use the word mips the way you did as you are talking about a text book not about a productized design, if their design still sticks to that pipe then that may be why arm just walked right past then and took over the world when mips coulda/shoulda) to not have any stalls or hazards, but not have such a latency (100 stages total completion of one instruction 100 clocks), so you balance the stalls and other issues with latency or time in the pipe. Time to re-fill the pipe on a branch.

So there is waste absolutely, by design, but just like you can create a benchmark to show the waste of the pipe, the slowness of a cache, the performance lost due to a branch prediction. Likewise if you dont like a pipeline and want to process one instruction at a time, it is far easier to make benchmarks to find the performance flaws in that where a pipe even with waste is faster, for that benchmark. Depending on what your degree is and classes you are taking if a computer engineer basically you may be tasked with a serial mips design and a parallel design and you can use your own implementations to demonstrate serial vs parallel with the same instruction sequence.

short answer other than specific cases, in general the instruction cant skip a step because something is there using that logic. That logic can only process one at a time. There are and have been many ways to help with this. Remember you are reading a textbook for educational purposes to try to understand the fundamentals.