According to the book Computer Organization and Design by Patterson and Hennessy (5th edition) page 304, the RegDst control signal is being used in the execution stage of the datapath. It acts as the selection bit for the mux that chooses the destination register from one of the two register addresses passed in the ID/EX pipeline register.
Why the RegDst control signal and the associated mux are not put in the instruction decode stage (the stage immediately before the execution stage)? That way, we could have sent only the selected destination register address from [20-16] and [15-11] bits of the instruction in the ID/EX pipeline register, instead of sending both of them.
