Do the core::arch::aarch64 functions vld1q_u8 and vst1q_u8 have any alignment requirements? The documentation doesn't mention any, but the documentation is also very sparse, so I'm wondering if there is one that's just not documented. I'm not sure how to figure out from the ARM documentation whether any such requirement exists.
Do these aarch64 intrinsics have alignment requirements?
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1 Answers
vld1q_xxx / vst1q_xxx are wrappers around SIMD vld1/vst1 instructions.
For details look armv8 documentation vld1
But shortly, address should be aligned to element size, in your case of reading bytes, it's 1 byte. In case of 16b data, 2 bytes, etc
So rule of thumb follow element size alignment.
As a side note, vld/vst support unaligned access, but it might be disabled by system. Refer SCTLR register for that.
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