is fcvtzs d0,d0 really an AArch64 SIMD instruction?

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gcc seems to classify fcvtzs d0,d0 as as SIMD instruction, but clang does not. Who is right?

$ cat toto.s
    fcvtzs d0,d0
$ aarch64-linux-gnu-gcc-10 -mcpu=cortex-a53+nosimd -c toto.s
toto.s: Assembler messages:
toto.s:1: Error: selected processor does not support `fcvtzs d0,d0'
$ clang -target aarch64-linux-gnu -mcpu=cortex-a53+nosimd -c toto.s
arm64 instructions instruction-set simd assembly
1 Answers

You’re far in to the arcane classification of instructions as practically speaking FP and Advanced SIMD are always available together.

I would read the Arm definition of FCVTZS as supporting GCC’S classification of the SISD form of FCVTZS (reading and writing D registers) as an instruction that requires +simd. The reasoning would be the encoding class of the instruction (Scalar single-precision and double-precision) and the shared pseudo-code calling CheckFPAdvSIMDEnabled64.

I say the question gets a bit arcane, because the architecture pseudocode definition of CheckFPAdvSIMDEnabled64 looks like this!

AArch64.CheckFPAdvSIMDEnabled()
    AArch64.CheckFPEnabled();

One technicality; your error message comes from the assembler not GCC; until recently these two tools also disagreed with each other.

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