Assign a hierarchical path to a string variable inside generate block for N number of instances

user_19350474 0
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I want to assign a hierarchical path to a string variable inside a generate block for N number of instances. Please let me know if it can work. I'm getting errors for hier assignment.

xmvlog: *E,EXPLPA (testbench.sv,17|9): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
      sub.str = `STRINGIFY(`HPATH);

This is the code I have tried:

module test;
  
`define STRINGIFY(x) `"x`"
`define HPATH top.chip.block
    subtest sub[3]();
  string hpath;
  
  initial begin
    hpath = `STRINGIFY(`HPATH);
    $display("HPATH is %s", hpath);
  end
  genvar r;
  generate
    for (r=0;r<2;r++)begin
      sub[r].str = `STRINGIFY(`HPATH);
    end
  endgenerate
endmodule

module subtest();
  string str;
  initial begin
    $display("%s",str);
  end
  
endmodule
system-verilog for-loop
1 Answers

The assignment you are trying to make is a procedural assignment, which means it must be inside a procedural block, like initial:

for (r=0;r<2;r++)begin
    initial sub[r].str = `STRINGIFY(`HPATH);
end

To avoid a race condition and guarantee that you will see the assigned string value in the subtest module, add some delay to the $display:

  initial begin
      #1 $display("%s",str);
  end
user_1977580
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