I am implementing a single cycle (one instruction per cycle) CPU in verilog. The CPU should support RISC-V add, lw, sw, beq instructions.
The problem is, when the instruction beq is decoded, the instruction after beq has already been in the pipeline and will be executed, no matter what the comparison result is.
RISC-V specification says there should be no delay slots. How can I achieve that, without breaking the one instruction per cycle design rule?