How to write a Muller C Element in Chisel Scala Language for async circuit?

user_19238407 0
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When I wrote this :


class MullerC(val WIDTH: Int = 2) extends Module {
  val io = IO(new Bundle {
    val in = Input(Vec(WIDTH, Bool()))
    val out = Output(Bool())
  })

  io.out := false.B
  when (io.in.reduce(_ & _)) {
    io.out := true.B
  }.elsewhen (io.in.map(!_).reduce(_ & _)) {
    io.out := false.B
  }
}

I got Verilog like this :

module MullerC(
  input   clock,
  input   reset,
  input   io_in_0,
  input   io_in_1,
  output  io_out
);
  assign io_out = io_in_0 & io_in_1;
endmodule

That is a simple and gate instead of a C gate.

But when I tried to add otherwise like this :


class MullerC(val WIDTH: Int = 2) extends Module {
  val io = IO(new Bundle {
    val in = Input(Vec(WIDTH, Bool()))
    val out = Output(Bool())
  })

  io.out := false.B
  when (io.in.reduce(_ & _)) {
    io.out := true.B
  }.elsewhen (io.in.map(!_).reduce(_ & _)) {
    io.out := false.B
  }.otherwise {
    io.out := io.out
  }
}

It could not be compiled any more:

Exception in thread "main" firrtl.transforms.CheckCombLoops$CombLoopException: : [module MullerC] Combinational loop detected:
MullerC.io_out
MullerC._GEN_0   @[----.scala 14:38 ----.scala 15:12 ----.scala 17:12]
MullerC._GEN_1   @[----.scala 12:30 ----.scala 13:12]
MullerC.io_out

How should I implement the Muller C in Chisel? Many thanks.

chisel asynchronous scala
1 Answers

I found the answer via this link: Disable FIRRTL pass that checks for combinational loops

I should use otherwise and then add --no-check-comb-loops as a parameter to emit verilog code. Thanks.

By the way, I also tried this and it works as well.

class MullerC(val WIDTH: Int = 2) extends Module {
  val io = IO(new Bundle {
    val in = Input(Vec(WIDTH, Bool()))
    val out = Output(Bool())
  })

  io.out := false.B
  val allTrue = Wire(Bool())
  val allFalse = Wire(Bool())

  allTrue := io.in.reduce(_ & _);
  allFalse := io.in.map(!_).reduce(_ & _)
  io.out := Mux(allTrue | allFalse, Mux(allTrue, true.B, false.B), io.out)
}

This will generate more beautiful verilog code althought it does not matter.

user_192384070
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