What's the meaning of "under" in phrase "hit-under-miss"?

user_2947904 0
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ARM website contains an explanation of a feature called "HUM" (hit-under-missing).

It seems that "under" can be interpreted as "after" or "follow", meaning that the previous access is a miss, and the subsequence access is a hit. Is this understanding correct? And if, I am wondering is there special context for using the word "under" (i.e., use spatial-relationship instead of time-relationship).

arm caching
2 Answers

The word "under", in this case, probably means "during" or "while", as in "hit during (under the circumstances of recovering from a previous) miss".

The intent is to let the load/store unit continue accessing memory freely while it waits for a line fill (transfer from cache-capable memory to the cache) to recover from a previous miss. There is no need to stall while there are no subsequent misses:

Advancing time =======================>

hit hit miss/line-fill ------> carry-on
             hit hit hit hit >

However, a stall will happen if a miss occurs while a line-fill is currently being performed. At that point, no further action will take place until the first line-fill completes, at which point the stall will "un-stall" and the next line-fill will start (alongside any non-misses):

Advancing time ================================================>

miss/line-fill --------> carry-on
     hit miss/stall ...> line-fill ----> carry on
                         miss/stall ...> line-fill ---> carry on
                                         hit hit ----->

Perhaps a more graphical way of viewing this is in the following simplified block diagram:

          +--------+
      +-> | dcache | <---+ linefile
      |   +--------+     | (via amba)
      V             +----------+
+------------+      | cachable |
| load/store |      |  memory  |
|    unit    |      +----------+
+------------+
      ^         +--------------+
      |         | non-cachable |
      +-------> |    memory    |
                +--------------+

Once a line-fill starts, there is no stall provided the load/store unit only reads:

  • cachable memory that's already in the dcache; or
  • non-cachable memory.
user_148600

Prior to ARMv6, the whole pipeline stalled if a cache-miss occured.
HUM means that independent instructions keep being executed even if a cache-miss occurs.

1:
ldr r0, [r10], #4
lsl r1, r1, #2
subs r9, r9, #1
add r1, r0, r1
bgt 1b

no HUM: the next instruction lsl gets executed AFTER the cache-miss penalty (dozens of cycles) HUM: the first dependent instructionadd has to wait. Prior instructions lsl and subs get executed regardlessly.

user_10215040
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