Instantiation of a class doesn't work (Chisel/Scala)

user_14822429 0
Viewed 31

I got the following error:

java.lang.IllegalArgumentException: requirement failed: must be inside Builder context

issue when I write this on the terminal : sbt run

This is my code:

import chisel3._

class combinedTausworthe extends Module {
  val io = IO(new Bundle {})
  val seed1 = RegInit(322769304.U(32.W))
  val seed2 = RegInit(424235419.U(32.W))
  val seed3 = RegInit(212119443.U(32.W))
  var result = 0.U

  var b = ((seed1 << 13)(31, 0) ^ seed1)
  seed1 := ((seed1 & 4294967294L.U) << 12)(31, 0) ^ b
  b := ((seed2 << 2)(31, 0) ^ seed2) >> 25
  seed2 := ((seed2 & 4294967294L.U) << 4)(31, 0) ^ b
  b := ((seed3 << 3)(31, 0) ^ seed3) >> 11
  seed3 := ((seed3 & 4294967294L.U) << 17)(31, 0) ^ b

  result := (seed1 ^ seed2 ^ seed3)
  println(result)

}

object Main extends App {
  val variable = Module(new combinedTausworthe())
}
chisel scala
1 Answers

For instantiation of the top of your design, you need to invoke ChiselStage or some other entry-point function.

If you wish to compile and dump Verilog, try:

object Main extends App {
  emitVerilog(new combinedTausworthe) // this was added in v3.5.0
  
  // If you are using a version older than v3.5.0, use the following
  (new chisel3.stage.ChiselStage).emitVerilog(new combinedTausworthe)
}

If you wish to just get a String that you can print, try the following:

object Main extends App {
  println(getVerilogString(new combinedTausworthe)) // this was added in v3.5.0
  
  // If you are using a version older than v3.5.0, use the following
  println(chisel3.stage.ChiselStage.emitVerilog(new combinedTausworthe))
}
user_24833290
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