Do I have to specify both stage flags to ensure the proper memory invalidation?

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If I issue a transfer command, and then want to read that data from the shaders (both vertex and fragment), I'd do like this:

cmd_buffer->issueTransferCommand();
PIPELINE BARRIER
srcStageMask = VK_PIPELINE_STAGE_TRANSFER_BIT;
srcAccessMask = VK_ACCESS_WRITE_BIT; /* flush the transfer writes */
dstStageMask = VK_PIPELINE_STAGE_VERTEX_SHADER_BIT;
dstAccessMask = VK_ACCESS_READ_BIT; /* invalidate the caches from the point of view of the vertex shader */

Do I have specify the invalidation of the caches for the fragment shader stage as well?

1 Answers

Yes, all pipeline stages must be explicitly included for the purposes of memory dependencies.

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