How does SystemVerilog compiler knows to separate two arguments in a macro?

user_2145043 0
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I have this macro:

`define do_code(DO_SOETHING, ID) \
    fork \
       begin \
          ``DO_SOMETHING`` \
       end \
       begin \
          $display("%s",ID.name()); \
       end \
    join_any \
    disable fork; \

and I use it as such:

`do_code($display("%s",argA.name()), argB)

How does the compiler knows to separate the two macro's input arguments correct:

DO_SOMETHING = $display("%s",argA.name())
ID = argB

Why not break it to:

DO_SOMETHING = $display("%s"
ID = argA.name()), argB

???

system-verilog macros
1 Answers

The compiler knows because the IEEE 1800-2017 SystemVerilog LRM says in section 22.5.1 `define

Actual arguments and defaults shall not contain comma or right parenthesis characters outside matched pairs of left and right parentheses (), square brackets [], braces {}, double quotes "", or an escaped identifier.

The comma in your fist argument is inside a matched pair of parenthesis.

BTW, you should not be using `` unless you are trying to create a new identifier by joining macro argument with text in the body of the macro,

user_27556070
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