UVM Verbosity override

user_472485 0
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Is there a way to override any verbosity switches that have been given and force verbosity to a different value in UVM?

+uvm_set_verbosity=*abc*,_ALL_,UVM_FULL,run 
+uvm_set_verbosity=*aes*,_ALL_,UVM_FULL,run 
+uvm_set_verbosity=*sel*,_ALL_,UVM_FULL,run 
+uvm_set_verbosity=*init*,_ALL_,UVM_FULL,run

For example if cmdline has these switches, what is the easiest way to quiet all these high verbosity without removing individual switches?

uvm system-verilog
1 Answers

Hunting around in the source code of UVM I found the set_report_verbosity_level_hier function in uvm_component. You could call that on uvm_root and set it (quite indiscriminately) to whatever low value you fancy.

initial begin
    uvm_root root;
    root = uvm_root::get();
    root.set_report_verbosity_level_hier(UVM_LOW);
    // Whatever you do here.
end

If you want to do that only for some ids you should be able to do that with set_report_id_verbosity_hier.

Notice I just tested the snippet above in a dumb testbench without even a test, so it might have problems with a real-world setup. If you have a more complex phasing of verbosity settings for your components you will need to override them each time they are applied, or toy with m_verbosity_settings directly.

user_77988210
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