Will an If statement stop checking if the first OR condition is met?

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Does SystemVerilog evaluate the whole if statement or the minimum to get the result?

For example:

if (condition1 && condition2) begin
  ...
end

if (condition1 || condition2) begin
  ...
end

In the first case, will condition2 be evaluated if condition1 is False? In the second case, will condition2 be evaluated if condition1 is True?

system-verilog if-statement
1 Answers

This behavior is also known as short-circuit evaluation.

Refer to IEEE 1800-2017, section 11.4.7 Logical operators.

The && and || operators shall use short circuit evaluation as follows:
    — The first operand expression shall always be evaluated.
    — For &&, if the first operand value is logically false then the second 
      operand shall not be evaluated.
    — For ||, if the first operand value is logically true then the second 
      operand shall not be evaluated.

Therefore, for the operators in your if statements, all the expressions may not be evaluated.

To see which operators have similar behavior, and which do not, refer to section 11.3.5 Operator expression short circuiting.

user_1977580
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